PowerQUICC
Power-On Reset
The PQII (MPC82xx) uses 32-bit of data (configuration
word) to initialized critical parameters during power-on reset.
The PQIII can use the content of non-volatile memory (normally
flash memory) to initialized critical parameters (more than
four bytes) using I2C serial interface.
How
the PowerQUICC Buffer Descriptors work
Transmit buffer descriptors and receive buffer descriptors
are the "road signs" that describe how serial channels
(including DMAs) move data to and from the device. Learn how
BDs operate.
How
the PowerQUICC DMA Basic Direct Mode Works
The PQIII hardware DMA has a more sophisticated DMA capabilities
compared with its predecessors. For backward compatibility
and legacy issues the basic direct mode is also supported.
Learn to see how it works.
How
the PowerQUICC Stashing Works
Stashing allows data from an IO master ( PCI, TSEC, RIO,
DMA, CPM) to be allocated in L2 cache while simultaneously
being written to memory (DDR SDRAM). Stashing allows
the e500 core to quickly access data from L2 cache (fast)
without going to DDR SDRAM memory.
Big-Endian,
Little-Endian, Power Architecture Little-Endian Explained
(Byte Ordering)
In our instructor-led training classes, we observed students
are still confused and perplexed by the various byte ordering
scheme available.
We do encourage students/designers to use big endian since
it is the predominant byte ordering supported by Power Architecture
systems. However, for students coming from a “different”
architecture it is a struggle. In this animation, we try to
explain the differences and hopefully students/designers will
be better equipped to select which mode of byte ordering they
should use.
How
the I2C Bus Works 
I2C is a multi-master serial bus invented by Philips®
that is used to attach low-speed peripherals to a Power Architecture
devices. Learn how I2C works at your own pace. This
short tutorial is improved since audio is incorporated to
facilitate the learning experience. Go check it out.
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