PhoenixMicro is pleased to provide our "Designing with" On-line Series of Workshops. We are confident you will find them productive for engineers who are designing and developing systems based on the architecture in the workshop. This Series of on-line workshops is an excellent reference which extends our open-enrollment and in-plant courses.

 

ON-LINE MINI ANIMATION TRAINING WORKSHOP
 
Check out our PowerQUICC mini animation workshops. Over time, we have noticed that as the PQ family becomes more sophisticated, students attending the class need to have "targeted" prerequisites to make the class more effective. Students need to understand basic knowledge in order to have a successful class, but how do we make it fun and simple?

Well, what we have done is designed mini animation series to prepare students fulfill these prerequisites and therefore, have an effective training environment.

Browse our free mini animation series and starts your learning adventure properly by enrolling in one of our classes.

PowerQUICC Power-On Reset
The PQII (MPC82xx) uses 32-bit of data (configuration word) to initialized critical parameters during power-on reset. The PQIII can use the content of non-volatile memory (normally flash memory) to initialized critical parameters (more than four bytes) using I2C serial interface.

How the PowerQUICC Buffer Descriptors work
Transmit buffer descriptors and receive buffer descriptors are the "road signs" that describe how serial channels (including DMAs) move data to and from the device. Learn how BDs operate.

How the PowerQUICC DMA Basic Direct Mode Works
The PQIII hardware DMA has a more sophisticated DMA capabilities compared with its predecessors. For backward compatibility and legacy issues the basic direct mode is also supported. Learn to see how it works.

How the PowerQUICC Stashing Works
Stashing allows data from an IO master ( PCI, TSEC, RIO, DMA, CPM) to be allocated in L2 cache while simultaneously being written to memory (DDR SDRAM). Stashing allows the e500 core to quickly access data from L2 cache (fast) without going to DDR SDRAM memory.

Big-Endian, Little-Endian, Power Architecture Little-Endian Explained (Byte Ordering)
In our instructor-led training classes, we observed students are still confused and perplexed by the various byte ordering scheme available.
We do encourage students/designers to use big endian since it is the predominant byte ordering supported by Power Architecture systems. However, for students coming from a “different” architecture it is a struggle. In this animation, we try to explain the differences and hopefully students/designers will be better equipped to select which mode of byte ordering they should use.

How the I2C Bus Works
I2C is a multi-master serial bus invented by Philips® that is used to attach low-speed peripherals to a Power Architecture devices. Learn how I2C works at your own pace. This short tutorial is improved since audio is incorporated to facilitate the learning experience. Go check it out.

 

DISCLAIMER: Topics discussed are short tutorials showing overall functionalities and concepts. These animations may not contain complete discussions , and are not substitutes to actual reference manuals. 


 
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