AMCC PPC440 Processor Core

The PPC440 contains a dual-issue, superscalar, pipelined processing unit along with other functional elements. Such as MMU, Cache control, timers, debug facilities. Interfaces for custom co-processors and floating point functions are provided. Along with separate instruction and data cache array interfaces which can be configured to various sizes. The PLB has been extended to 128 bits and is fully compatible with IBM® CoreConnect on-chip system architecture, providing the framework to efficiently support SOC designs.

Documents.

Download the latest PPC440 rev1.09 March 13, 2008

Audience:

The PPC440 processor class is designed for software, hardware, firmware, test engineers, and system developers who want to build high-bandwidth bridges, switches, telecommunications, and data communications system. The PPC440 core can be utilized as superscalar host processor or pre-processor engine for various other applications. System architects, project leaders, and BSP  designers who want to understand device architecture are also encourage to attend the class for an in-depth knowledge.

PPC440 Course Agenda:

The class that will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the PPC440 architecture and pipeline structures.
  
• Recognize the programming model, register types, and usage.
  
• Review instruction set, branches and subroutine calls.
  
• Understand and learn synchronizing instructions, extended mnemonics.
  
• Learn how the PPC440 core accesses operand in memory. Can cause a lot of problems if not learned correctly (GPR0).
  
• Write efficient interrupt routine service by understanding how exception processing works, and how to nest interrupts.
  
• Understand PPC440 instruction cache and data cache. How to configure and optimize them for your single and multi-master applications.
  
• Configure the Memory Management Unit (MMU) to perform address translation and enable access control and protection.
  
• Learn the various PPC440 core interfaces such as the Processor Local Bus (PLB), the Device Control Register (DCR) interface, and the Auxiliary Processor Unit (APU) interface.
  
• Understand PPC440 hardware pipelining and split bus transaction. Learn how these features can enhance your design performance.
  
• Review the DSP instructions, which can help facilitate and optimize signal processing applications.
  
• Review the various PPC440 core Debug Facilities supported.
  
• Learn how to program the various PPC440 CPU timers such as Timebase, Decrementer, Fixed Interval Timer (FIT), and the Watchdog timer.
  
• Configure and learn how to initialize the PPC440 core from power-on reset.
  

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Prerequisite:

Understanding of a general CISC processor is helpful. Also, familiarity with other RISC processors such as MIPS or ARM core, or equivalent is preferred. However, student’s willingness and desire to learn is the most important factor.

Fee and Registration:

• Payment must be received no later than one week prior to start of course. The fee includes course notes, Rerence Manuals, and other applicable application notes and handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.