The MPC8240/41/45 Power Architecture Microcontroller
The MPC8240/41/45 Integrated Processor consists
of Power Architecture 603e processor core with Floating-Point support,
Memory Management Unit (MMU), 16-Kbyte Instruction Cache,
and 16-Kbyte Data Cache. It also has 32-bit PCI Interface,
Memory Controller, Two-channel DMA Controller, Messaging Unit,
I2C Interface and programmable Interrupt Controller, two (dual)
universal asynchronous receiver/transmitters (UARTs).
What is the difference among the MPC8240/41/45?
The MPC8245 s a second generation
MPC8240 with a G2 PPC Core (603e) and a PCI bridge. Many of
the enhanced features of the MPC8245 can be found in the peripheral
logic block. The MPC8241 is a low cost version of the MPC8245.
The class will mainly focus on the MPC8245. Download
this pdf file to view detailed comparison and compatibility
between MPC8240 and MPC8245 devices.
Audience:
The MPC8240/41/45 course is designed
for Software and Hardware engineers and developers who want
to build systems using PCI interfaces in networking, routers,
switches, network storage applications and image display systems
and other embedded applications. System architects, project
leaders, and BSP designers who want to understand device architecture
and requirements are also encourage to attend the course for
an in-depth understanding of the silicon system.
MPC8240/41/45 Course Agenda:
The class will cover both hardware
and software aspect of the MPC8240/41/45 device. Each topic
is self-contained. That is, both hardware and software discussions
are included to make the topic complete. The course is consists
of lectures and exercises.
- Overview of the MPC824x architecture
series.
- Recognize the 603e programming
model, register types, and usage.
- Review 603e instruction set,
branches, subroutine calls, simplified mnemonics, and accessing
operand in memory.
- Write efficient interrupt
routine service by understanding how exception processing
works, and how to nest interrupts.
- Understand MPC824x instruction
cache and data cache. How to configure and optimize them
for your application.
- Configure the memory management
unit (MMU) to perform address translation and enable access
control and protection.
- Initialize the MPC824x configuration
registers.
- Configure address mapping
for 603e and PCI accesses.
- Program the interrupt controller
to prioritized interrupts for PPC 603e processing.
- Utilize the memory controller
to handle various types of static and dynamic memories.
- Initialize the PCI controller
to arbitrate, perform exclusive accesses, boot ROM relocation,
and maximize PPC603e and PCI memory throughput.
- Enable the various power saving
modes of the MPC824x device.
- Use various debug features
such as identifying PCI transactions, inject stuck-at-faults,
data capture on parity error.
- Program the I2C controller
to perform serial, full-duplex, master/slave operation.
- Configure the Message Unit
and Intelligent to perform doorbell function, In-bound/Out-bound
messaging.
- Two (dual) universal asynchronous
receiver/transmitters (UARTs).
Note:
Total number of topics covered will vary depending on course
size, student's background, and pace of the course. Our instructors
are flexible to adapt and adjust topics to suit your requirements.
Prerequisite:
Understanding of a RISC processor
is helpful. Knowledge of PCI interface is advantageous. However,
student’s willingness and desire to learn are the most
important factors.
Fee and Registration:
|