The MPC8280, MPC82xx PowerQUICC II Power Architecture Host Processor

The MPC8280, MPC82xx PowerQUICC II (Power Quad Integrated Communications Controller - Second Generation) is a single-chip, highly integrated microcontroller. It has a 32-bit RISC Power Architecture 603e (G2-type EPPC) as a host processor and another dedicated 32-bit RISC communication processor (CP) plus a System Interface Unit (SIU) for communication and networking applications.

Document

Download the latest MPC8280RM rev1 (12/2005) and the latest MPCFPE32B rev3 (9/2005).

Audience:

The MPC8280, MPC82xx PowerQUICC II training course is designed for software, hardware engineers, and developers who want to build communication and networking applications. System architects, project leaders, and BSP designers who want to understand device architecture and requirements are also encourage to attend the class for an in-depth understanding of the silicon system.

MPC8280, MPC82xx Course Agenda:

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Understand the overall Architecture of the MPC8280, MPC82xx family of devices.
  
• Review G2 Core Programming Model, register types, and usage.
  
• Learn the G2 core instruction set, branches, subroutine class. Also, learn how to access operands in memory.
  
• Undertand the G2 various caching modes for its I-cache and D-cache. Learn how use these modes to optimize your system design.
  
• Configure the G2 memory management unit (MMU) for system level protection and address translation functions.
  
• Learn how to calculate serial channel communication performance, such as FCCs and MCCs, based on your applications.
  
• Initialize the Fast Communication Controllers (FCCs) to transmit and receive HDLC packets, Fast Ethernet frames, and ATM cells.
  
• Program the communication processor interrupt controller (CPIC) to recognize and prioritize interrupt sources.
  
• Write exception service routine (ESR) to service various serial communication channels.
  
• Learn how to set up the the Time Slot Assigner (TSA) for Time Division Multiplexing (TDM) and non-multiplexing serial interface (NMSI) function.
  
• Configure Multi-Channel Controllers (MCCs) for HDLC and Transparent protocols for up to 128 channels per MCC.
  
• Program the memory controller to interface to static memories (SRAM, flash, ROM, EEPROM) and dynamic memories (DRAM and SDRAM) using GPCM, UPM, and SDRAM controllers.
  
• Understand how to initialize the MPC82xx from power-on reset.
  
• Learn how the 60x bus works and how to interface external peripherals.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Prerequisite:

Understanding of MC68360, or MPC8xx is helpful. Also, familiarity with C language especially data structure organization is advantageous. However, student’s willingness and desire to learn are the most important factors.

Fee and Registration:

• Payment must be received no later than one week prior to start of course. The fee includes course note, MPC82xx user manual, Power Architecture microprocessor family programming environment, and other applicable handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.
  

  Note:For pricing and availability for an ON-SITE course please use the ON-SITE Request Form.