The MPC8313E PowerQUICC II™ PRO Power Architecture Host Processor

The MPC8313E PowerQUICC II Pro is a low-power, single-chip, highly integrated system on a chip. It has a 32-bit RISC Power Architecture e300c3 core with 16Kbytes of instruction and 16Kbytes of data cache, dual three-speed Ethernet controllers (eTSECs), a DDR1/DDR2 SDRAM memory controller, enhanced local bus controller (eLBC), 32-bit PCI-2.3 controller, dual I2C controllers, a 4-channel DMA controller, USB 2.0 host and device controller with an on-chip, high-speed USB 2.0PHY, and much more.

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Download the latest MPC8313E (rev2 12/2008) and the latest e300 Core RM rev4 (12/2007)

Audience:

The MPC8313E PowerQUICC™ II Pro training course is designed for software, hardware, firmware, test engineers, and developers who want to build wireless LANs, network access servers, VPN routers, intelligent NICs, and industrial controllers. System architects, project leaders, and BSP designers, device driver designers, test engineers who want to understand device architecture and requirements are also encourage to attend the class for an in-depth understanding of the silicon system.

MPC8313E Course Agenda:

The class is a 3-day class that will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional descriptions of the MPC8313E and MPC8313 PowerQUICC™ II Pro architecture.
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation and Mapping.
• Learn the latest e300c3 core programming model, register types, and usages and how it is different from the e300c1 and e300c2 versions.
• Review e300c3 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
• Configure and optimize the e300c3 L1 16Kbytes of Instruction and 16 Kbytes of data cahce (Harvard architecture) to suit your application.
• Initialize the e300c3 core Memory Management Unit to perform address translation, access control, and protection
• Write efficient exception service routines for the e300c3 and Integrated Programmable Interrupt Controller (IPIC) by understanding the improved exception processing function with separate critical and non-critical interrupts.
• Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs operation, TCP/IP offload, Quality of Service (QoS) support, interrupt coalescing, RMON statistic support, HW assist for 1588 compliant time stamping, core snoop attributes, power management using AMD Magic Packet protocol™.
• Program the enhanced Local Bus Controller (eLBC) for local memory functions including Flash Control Machine (FCM), SRAM, flash EPROM, and EPROM using General
• Purpose Chip Select Machine (GPCM), and DRAM memories using User Programmable Machine (UPM).
• Configure and initialize the advanced main memory controller for DDR1/DDR2 SDRAM memories.
• Configure and initialize the 32-bit PCI (compatible with PCI Local Bus Specification, Rev 2.3) controller module.
• Program and initialize the DMA controller to transfer data between two processors on different buses.
• Learn how to initialize the MPC8313E from power-on reset.
• Understand how the Security Engine (SEC2.2) can off-load computation intensive security functions.
• Configure the other controllers such as I2C, DUART, SPI and USB to perform data transfer.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit the requirements.

Prerequisites:

Understanding of MPC82xx, or MPC8xx is helpful. Also, familiarity with C language especially data structure organization is advantageous. However, student’s willingness and desire to learn is the most important factors.

Fee and Registration:

• Payment must be received no later than one week prior to start of course. The fee includes MPC8313E course note, MPC8313ERM, e300Core RM, Power Architecture microprocessor family programming environment, and other applicable application note handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.
  

  Note: For pricing and availability for an ON-SITE course please use the ON-SITE Request Form.