The MPC8323E PowerQUICC II PRO Power Architecture Host Processor

The MPC8323E PowerQUICC II Pro is a single-chip, highly integrated SOC system. It has a 32-bit Power Architecture™ e300c2 Core with dual integer units but no FPU) as a host processor. The MPC8323E family incorporates the next-generation communication engine, the QUICC® Engine, supporting protocols such as Fast Ethernet, HDLC, ATM up to OC-3 speed. The MPC8323E device also contains, DDR/1 or DDR/2 memory controller, a Local Bus Controller, 32-bit PCI controller, Programmable Interrupt Controller, 4-channel DMA and many more peripherals for embedded communication and networking applications.

Document

Download the latest MPC8323ERM (rev2 10/2008)

Audience:

The MPC8323E PowerQUICC II Pro training course is designed for software, hardware, firmware, test engineers, and developers who want to build communication and networking applications. System architects, project leaders, and BSP designers who want to understand device architecture and requirements are also encourage to attend the class for an in-depth understanding of the silicon system.

MPC8323E Course Agenda:

The class is a 4-day class that will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the functional description of the MPC8323E architecture and other derivatives.
  
• Understand the internal memory map structure including Local Access Windows (LAWs) and Inbound/Outbound Address Translations.
  
• Learn the latest e300c2 core programming model, register types, and usages and how it is different from the 603e or e300 core.
  
• Review the e300c2 instruction sets, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
  
• Write efficient exception service routines for the new e300c2 and Integrated Programmable Interrupt Controller (IPIC) by understanding the innovative exception processing function with interrupt priorities, separate critical interrupt and non-critical interrupt signals.
  
• Configure and optimize the e300c2 16 Kbytes of instruction cache and 16 Kbytes of data cache to suit your application.
  
• Initialize the memory management unit (MMU) to perform address translation and enable access control and protection.
  
• Understand how the QUICC Engine utilizes the SDMA and how to configure the enhanced Parameter RAM.
• Configure and initialize the UCC for HDLC Controller to transmit and receive Ethernet frames .
• Configure and initialize the UCC for Ethernet Controller to transmit and receive Ethernet frames at 10 and 100 Mbps with MII and RMII support.
  
• Configure and intialize the UCC to function as an ATM controller to process AAL0 and AAL5 cells.
  
• Program and set up the Serial Interface (SI) for TDM operation and QMC functions.
  
• Configure and initialize the advanced 32-bit DDR1 or DDR2 memory controller
  
• Configure and initialize the 32-bit Local Bus Controller to interface to static memory and DRAM-type memory using GPCM and UPM machines.
  
• Configure and initialize the 32-bit PCI controller block.
  
• Configure and initialize the DMA controller, SPI, I2C, DUART, USB modules.
  
• Understand how the Security Engine Block (SEC 2.2) works.
• Configure and initialize the reset controller to detect/generate internal reset.
• Understand how the Security Engine Block (SEC 2.2) works.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit the requirements.

Prerequisites:

Understandings of MP82xx and data communication fundamentals are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, student’s willingness and desire to learn are the most important factors.

Fee and Registration:

• Payment must be received no later than one week prior to start of course. The fee includes course note, MPC832x user manual, Power Architecture microprocessor family programming environment, and other applicable handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.
  

  Note: For pricing and availability for an ON-SITE course please use the ON-SITE Request Form.