The MPC8360 PowerQUICC II PRO Power Architecture with Next-Generation QUICC™ Engine

The MPC8360E PowerQUICC II Pro is a single-chip, highly integrated SOC system. It has a 32-bit Power Architecture™ e300 Core) as a host processor The MPC8360E family incorporates the next-generation communication engine, the QUICC™ Engine, supporting protocols such as Gigabit Ethernet, OC-12 ATM/POS. The MPC8360E device also contains, DDR SDRAM memory controller, Local Bus Controller, PCI controller, Interrupt Controller, 4-channel DMA and many more peripherals for embedded communication and networking applications.

Documentations

Download the latest MPC8360RM rev2 (05/2007) and the latest e300 Core RM rev4 (12/2007)

Audience:

The MPC8360E PowerQUICC II Pro training course is designed for software, hardware, firmware, test engineers, and developers who want to build communication and networking applications using the next-generation QUICC™ Engine. System architects, project leaders, and BSP designers, device driver designers, test engineers who want to understand device architecture and requirements are also encourage to attend the class for an in-depth understanding of the silicon system.

MPC8360 Course Agenda:

The class is a 4-day class that will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the functional description of the MPC8360E architecture and other derivatives.
  
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation.
  
• Learn the latest e300 core programming model, register types, and usages and how it is different from the 603e core.
  
• Review e300 instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
  
• Write efficient exception service routines for the new e300 and Integrated Programmable Interrupt Controller (IPIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical interrupts and machine check signal.
  
• Configure and optimize the e300 instruction cache and data cache to suit your application.
  
• Initialize the memory management unit (MMU) to perform address translation and enable access control and protection.
  
• Understand how the QUICC Engine works and how it utilizes the SDMA and the enhanced Parameter RAM.
  
• Program the UCC (Unified Communication Controller) for Ethernet Controller to transmit and receive Ethernet frames at 10/100/1000 Mbps.
  
• Program the UCC to function as an ATM controller to process AAL0, AAL1, and AAL5 cells.
  
• Configure the enhanced Multi-Channel Controller (MCC) for various protocols.
  
• Configure the serial interface (SI) for TDM operation, MCC and QMC functions.
  
• Configure and initialize the advanced DDR SDRAM memory controller.
  
• Configure and initialize the Local Bus Controller to interface to static memory, DRAM memory, and SDRAM memory using GPCM, UPM, and SDRAM controllers respectively.
  
• Configure and initialize the integrated programmable interrupt controller (IPIC) to prioritize and recognize interrupt sources.
  
• Configure and initialize the DMA controller, SPI, I2C, DUART, USB modules.
  
• Configure and initialize the reset controller to detect/generate internal reset.
  
• Configure and initialize the PCI controller block.
  
• Understand how the Security Engine Block (SEC 2.0) works.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit the requirements.

Prerequisites:

Understanding of MPC834x, or MPC82xx is helpful. Also, familiarity with C language especially data structure organization is advantageous. However, student’s willingness and desire to learn are the most important factors.

Fee and Registration:

• A payment of US$1595.00 must be received no later than one week prior to start of course. The fee includes course note, MPC8360ERM, Power Architecture microprocessor family programming environment, and other applicable handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.
  

  Note: For pricing and availability for an ON-SITE course please use the ON-SITE Request Form.