The MPC8533E PowerQUICC III Power Architecture Processor

The MPC8533E PowerQUICC III class will cover MPC85xx family of Power Architecture processors. The MPC833E is a single-chip, highly integrated system on a chip. It has a 32-bit RISC Power Architecture e500v2 core (difference between e500v1 and e500v2 cores) as a host processor with on-chip 256-Kbyte of L2 Cache/SRAM memory module, enhanced Triple-Speed Ethernet Controllers (eTSECs), DDR2 memory controller, another Local Bus Controller for SDRAM, Flash type memories, 32-bit PCI, PCI Express, and much more.

Audience:

The MPC8533E PowerQUICC III class will cover MPC85xx family of devices. The course is designed for software, hardware, firmware engineers, and developers who want to build communication and networking applications. System architects, project leaders, BSP designers, device driver designers, and test engineers who want to understand device architecture and requirements are also encourage to attend the class for an in-depth understanding of the silicon system.

MPC8533E Course Agenda:

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional descriptions of the MPC85xx PowerQUICC architectures.
  
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
  
• Learn the latest e500v2 core programming model, register types, and usages and how it is different from the e500v1 version.
  
• Review e500v2 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
  
• Write efficient exception service routines for the new e500v2 and Programmable Interrupt Controller (PIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.
  
• Configure and optimize the e500v2 L1 caches and the L2 look-aside cache/static SRAM block (256Kbytes) to suit your application. Understand how "Stashing" and "Extraction" can be utilized with L2 cache to improve system performance.
  
• Initialize the enhanced two-level Memory Management Unit to perform address translation, access control, and protection.
  
• Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, Quality of Service (QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol™.
  
• Configure and initialize the advanced main memory controller for DDR2 type memories.
  
• Program the second memory controller using Local Bus Controller (LBC) for local bus functions including SDRAM (DRAM), SRAM, flash EPROM, and EPROM memory operations.
  
• Configure and initialize the 32-bit PCI, or the PCI Express controller modules.
  
• Program and initialize the DMA controller to transfer data between memories and I/O.
  
• Learn how to initialize the MPC8533 from power-on reset.
  
• Understand how the Security Engine (SEC) can off-load computation intensive security functions.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Prerequisite:

Understanding of MPC82xx, or MPC8xx is helpful. Familiarity with C language especially data structure organization is advantageous. However, student’s willingness and desire to learn are the most important factors.

Fee and Registration:

• Payment must be received no later than one week prior to start of course. The fee includes course notes, Rerence Manuals, and other applicable application notes and handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.