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The MPC85xx PowerQUICC III Power Architecture Host Processor
The MPC8560/40 PowerQUICC III (Power Quad Integrated Communications
Controller - Third Generation) is a single-chip, highly integrated
microcontroller. It has a 32-bit RISC Power Architecture e500 core (5th
generation) as a host processor, a communication processor
module (CPM), two triple-speed Ethernet controllers (TSEC),
DDR SDRAM memory controller, 64-bit PCI-X/PCI controller,
RapidIO™ interconnect and much more.
Audience:
The MPC85xx PowerQUICC
III training course is designed for software, hardware, firmware
engineers, and developers who want to build communication
and networking applications. System architects, project leaders,
BSP designers, device driver designers, and test engineers
who want to understand device architecture and requirements
are also encourage to attend the class for an in-depth understanding
of the silicon system.
MPC85xx Course Agenda:
The class will
cover both the hardware and software aspect of the device.
Each topic is self-contained. That is, both hardware and software
materials are included to make the topic complete. The class
consists of lectures and exercises.
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Overview
of the overall functional description of the MPC85xx family.
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Understand
the MPC85xx internal memory map structure and inbound/outbound
window mapping and address translation operation.
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Learn the
latest e500 core programming model, register types, and
usages.
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Review
e500 core instruction set, branches, subroutine calls,
simplified mnemonics, and accessing operand in memory.
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Write
efficient exception service routines to the new e500 programmable
interrupt controller (PIC) by understanding the innovative
exception processing function with built-in interrupt
priorities and separate critical interrupt path.
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Configure
and optimize the e500 L1 caches and the L2 look-aside
cache/static SRAM block to suit your application.
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Initialize
the new Book E two-level MMU architecture to perform address
translation and enable access control and protection.
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Configure
the dual TSEC for 10/100/1000 Mbps Ethernet operation.
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Understand
the RapidIO™ open standard and the RapidIO™
interconnect controller operation.
- Configure and initialize the
advanced DDR SDRAM memory controller.
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Program
and initialize the DMA controller to transfer data between
RapidIO and local address spaces.
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Configure
and initialize the 64-bit PCI-X/PCI controller module.
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Program
the CPM FCC module to transmit and receive HDLC packets,
transmit and receive Ethernet frames, and transmit and
receive ATM cells.
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Program
and initialize a second memory controller via Local
Bus Controller (LBC) for local bus functions for SDRAM
(DRAM), SRAM, flash EPROM, and EPROM memory operations.
- Configure and initialize the
CPM (MPC8560) Time Slot Assigner (TSA) for time division
multiplexing (TDM).
- Program the CPM Multi-Channel
Controller (MCC) for HDLC or Transparent protocol for up
to 128 channels per MCC.
- Learn how to initialize the
MPC85xx from power-on reset.
Note:
Total topics covered will vary depending on class size, student's
background, and pace of the class. Our instructors are flexible
to adapt and adjust topics to suit your requirements.
Prerequisite:
Understanding
of MPC82xx, or MPC8xx is helpful. Familiarity with C language
especially data structure organization is advantageous. However,
student’s willingness and desire to learn are the most
important factors.
Fee and Registration:
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Payment
must be received no later than one week prior to start
of course. The fee includes course notes, MPC8560/40 and
e500 Core Complex Rerence Manuals. Also, Power Architecture microprocessor
family programming environment, and other applicable handouts.
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Seating
is limited so please register early to get the desired
place and time.
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Course
cancellation is accepted one week prior to start of class.
If the student cancelled one week prior to course he/she
can elect to have course substitution for the same course
at different date.
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Student
substitution is accepted from same company.
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If student
did not cancel one week prior to class the student will
be charge the full rate.
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PhoenixMicro
Inc. has the right to cancel courses one week prior to
start date due to low enrollment.
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