The MPC856x PowerQUICC III Power Architecture Host Processor with a QUICC Engine

The MPC856x is a single-chip, highly integrated SOC system. It has a 32-bit RISC Power Architecture e500v2 core as a host processor with on-chip 512-Kbyte of L2 Cache/SRAM. The MPC856x family incorporates the next-generation communication engine, the QUICC™ Engine, supporting protocols such 10/100/1000 Ethernet, OC-12 ATM/POS. two enhanced Triple-Speed Ethernet Controllers (eTSECs), DDR/DDR2 memory controller, another Local Bus Controller for SDRAM, Flash type memories, a 32-bit PCI controller, either a 1x/4x SRIO or a x4/x2/x1 PCI Express interface, and much more.

Document.

Download the latest MPC8568ERM Rev 1 (6/2008) and the QUICC Engine RM Rev0 (10/2007)

Audience:

The MPC856x PowerQUICC III training course is designed for designers looking for increased performance requirements for broadband access applications including 3G/WIMAX/LTE basestations, RNC's, gateways, and ATM/TDM/IP equipment. System architects, project leaders, and BSP designers, device driver designers, test engineers who want to understand the device architecture and requirements are also encourage to attend the class for an in-depth understanding of the silicon system.

MPC856x Course Agenda:

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional descriptions of the MPC856x family.
  
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
  
• Learn the latest e500v2 core programming model, register types, and usages and how it is different from the e500v1 version.
  
• Review e500v2 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
  
• Write efficient exception service routines for the new e500v2 and Programmable Interrupt Controller (PIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.
  
• Configure and optimize the e500v2 L1 caches and the L2 look-aside cache/static SRAM block (512Kbytes) to suit your application. Understand how "Stashing" and "Extraction" can be utilized with L2 cache to improve system performance.
  
• Initialize the enhanced two-level Memory Management Unit to perform address translation, access control, and protection.
  
• Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, Quality of Service (QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol™.
  
• Understand how the QUICC Engine utilizes the SDMA and how to configure the enhanced Parameter RAM.
  
• Program the QE UCC for Ethernet Controller to transmit and receive Ethernet frames at 10/100/1000 Mbps.
  
• Program the QE UCC to function as an ATM controller to process AAL0, AAL1, and AAL5 cells.
  
• Configure the QE enhanced Multi-Channel Controller (MCC) for various protocols.
  
• Configure the QE serial interface (SI) for TDM operation and MCC and functions.
  
• Configure and initialize the advanced main memory controller for DDR1/DDR2 type memories.
  
• Program the second memory controller using Local Bus Controller (LBC) for local bus functions including SDRAM (DRAM), SRAM, flash EPROM, and EPROM memory operations.
  
• Configure and initialize the PCI and PCI Express controller modules.
  
• Program and initialize the four-channel DMA controller to transfer data between SRIO, PCI, PCIe, and LBC and local address spaces.
  
• Learn how to initialize the MPC854x from power-on reset.
  
• Learn basic steps to initialize the MPC856x from power-on reset.
  
• Understand how the Security Engine (SEC) can off-load computation intensive security functions.
  
• Understand the Serial RapidIO™ open standard and the RapidIO™ interconnect controller operation.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Prerequisite:

Understanding of PowerQUICC family is helpful. Also, familiarity with C language especially data structure organization is advantageous. However, student’s willingness and desire to learn is the most important factor.

Fee and Registration:

• Payment must be received no later than one week prior to start of course. The fee includes course notes, Rerence Manuals, and other applicable application notes and handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.