The MPC8572E PowerQUICC III Dual-Core e500 Power Architecture Processors

The MPC8572 is a single-chip, highly integrated SOC system. It has dual-core e500v2 Power Architecture processors with 32kB I/D cache per core, an on-chip 1MB L2 Cache/SRAM, Dual integrated DDR2/DDR3 SDRAM memory controller with ECC, Four enhanced Triple-Speed Ethernet Controllers (eTSECs), Single 10/100 FEC, Table Look Up Unit, Pattern Matching Engine, Security Engine (SEC3.0), another 32-bit Local Bus Controller for SDRAM, SRAM, Flash type memories, either a 1x/4x SRIO or a x8/x4/x2/x1 PCI Express interface, dual I2C, dual DMA, DUART and much more.

Documents.

Download the latest MPC8572ERM rev2 (5/2008) and the latest e500CoreRM rev1 (4/2005).

Audience:

The MPC8572E PowerQUICC® III dual-core Power Architecture™ processors training course is designed for designers looking to balance processor performance with I/O system throughput. System architects, project leaders, and BSP designers, device driver designers, HW/SW engineers, test engineers who want to understand the PowerQUICC III SoC device architecture are also encourage to attend the class for an in-depth understanding of the silicon system.

MPC8572E Course Agenda:

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional description of the MPC8572E.
  
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
  
• Learn the latest e500v2 (double precision floating point capability) core programming model, register types, and usages.
  
• Review e500v2 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
  
• Write efficient exception service routines for the new e500v2 and Programmable Interrupt Controller (PIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.
  
• Configure and optimize the e500v2 L1 caches and the L2 look-aside cache/static SRAM block to suit your application. Understand how "Stashing" and "Extraction" can be utilized with L2 cache to improve system performance.
• Initialize the enhanced two-level Memory Management Unit (MMU) to perform address translation, access control, and protection.
• Configure the enhanced TSEC (eTSEC) for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, Quality of Service (QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol™.
• Configure and initialize the advanced dual memory controller for DDR2/DDR3 type memories.
• Intialize and configure the Local Bus Controller (LBC) for local bus functions including SDRAM, SRAM, FLASH memory operations.
• Learn how the Table Look Up (TLU) offloads complex table searches and perform header inspections.
• Understand how the Pattern-Matching Engine handles regular expression matching, a deflate engine to manage file compression.
• Configure and initialize the PCI Express controller.
• Program and initialize the dual four-channel DMA controller to transfer date between SRIO, PCIe, DDR2/3 and LBC memory.
• Learn how to initialize the MPC8572 from power-on reset.
• Understand how the Security Engine (SEC3.0) can off-load computation intensive security functions.
• Understand the serial RapidIO™ open standard and the RapidIO™ interconnect controller operation.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Prerequisite:

Knowledge of RISC processors and some communication protocols are a must. Understanding of PQI or PQII family is helpful. Familiarity with C language, especially data structure organization is advantageous. However, student’s willingness and desire to learn is the most important factor.

Fee and Registration:

• Payment must be received no later than one week prior to start of course. The fee includes course notes, Rerence Manuals, and other applicable application notes and handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.