The MPC8641/D Dual-Core Power Architecture Host Processor

The MPC8641/D architecture training class will cover the MPC8641, MPC8641D family of Power Architecture processors. The MPC8641 is a single-chip, highly integrated system on a chip. It has a 32-bit RISC e600 core host processor with on-chip 1MB of L2 Cache. The MPC8641D has two e600 cores and two 1MB L2 cache. The MPC8641/D has four eTSECs, two DDR memory, another Local Bus Controller, up to two PCI Express interfaces, Serial RapidIO™ interconnect and much more.

Documents.

Download the latest MPC8641DRM rev2 (7/2008) and the latest e600CoreRM rev0 (3/2006).

Audience:

The MPC8641D training course is designed for software, hardware, firmware, test engineers, and developers who are looking to deliver breakthrough performance, connectivity and integration for embedded networking, telecom, military, storage and pervasive computing applications. System architects, project leaders, and BSP designers, device driver designers, test engineers who want to understand device architecture are also encouraged to attend the class for an in-depth understanding of the silicon system.

MPC8641/D Course Agenda:

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Functional description overview of the MPC8641 and MPC8641D Power Architecture architectures.
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
• Learn the latest e600 processor core programming model, register types, and usages.
• Review e600 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
• Configure and optimize the 32-Kbyte L1 eight-way set-associative Harvard architecture and the 1-MB L2 unified cache to suit your applications.
• Initialize the Memory Management Unit to perform address translation, access control, and protection.
• Review the AltiVec™ Technology that enables the Single Instruction Multiple Data (SIMD) feature.
• Write efficient exception service routines for the new e600 core and the Programmable Interrupt Controller (PIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical and non-critical interrupts.
• Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, header parsing, QoS support, VLAN insertion and deletion, RMON statistics support, interrupt coalescing, power management using AMD Magic Packet protocol™.
• Configure and initialize the dual 64-bit memory controllers (that's right, two memory controllers!) for DDR, DDR2 SDRAM memories. Up to 16 Gbytes per memory controller.
• Program a third memory controller using Local Bus Controller (LBC) for local bus functions including SDRAM, DRAM, SRAM, flash EPROM, and EPROM memory operations.
• Program and initialize the DMA controller to transfer data between local memory and IO ports. Such as the Serial RapidIO™ and PCI Express ports.
• Configure and initialize the DMA controller to transfer data between RapidIO and local address spaces.
• Understand the serial RapidIO Interface open standard and the RapidIO interconnect controller operation.
• Understand the PCI Express 1.0a compatible and PCI Express Interface.
• Configure and initialize the two I2C controllers, the two UART controllers (DUART).
• Learn how to initialize the MPC8641/D from power-on reset.
• Optimize and test your HW and SW designs using the performance monitoring capabilities of the device.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit the requirements. Onsite classes can be customized for topic discussions and for shorter duration.

Prerequisite:

Understanding of MPC85xx or MPC82xx or MPC744x is helpful. Also, familiarity with C language especially data structure organization is advantageous. However, student’s willingness and desire to learn are the most important factors.

Fee and Registration:

• Payment must be received no later than one week prior to start of course. The fee includes course notes, Rerence Manuals, and other applicable application notes and handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.