The QorIQ P2020 and P2010 Communications Processors

The P2020 is a single-chip, highly integrated SOC system. The P2020 has a dual-core e500v2 Power Architecture processors with 32KB I/D cache per core, an on-chip 512KB L2 Cache/SRAM, 32/64-bit DDR2/DDR3 SDRAM memory controller with ECC, Three enhanced Triple-Speed Ethernet Controllers (eTSECs), Security Engine (SEC3.1), another 32-bit Local Bus Controller for Static and Flash type memories, two 1x or one 4x SRIO, three PCI Express interface, USB2.0, dual I2C, dual 4-channel DMA, DUART, timers and much more.

Document.

Download the latest P2020RM - TBD

Audience:

The P2020 training course is designed for software, hardware, firmware, test engineers, and developers who want to build Symmetric or cooperative multiprocessing communication and networking applications. System architects, project leaders, and BSP designers, device driver designers, test engineers who want to understand device architecture and requirements are also encourage to attend the class for an in-depth understanding of the silicon system.

QorIQ P2020 Course Agenda:

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional descriptions of the P2020 and P2010 architectures.
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
• Learn the latest e500v2 core programming model, register types, and usages.
• Review e500v2 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
• Write efficient exception service routines for the new e500v2 and Programmable Interrupt Controller (PIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.
• Configure and optimize the 32KB L1 Instruction cache and 32KB Data cache for each e500v2 core to maximize performance.
• Configure and optimize the 512 KB L2 look-aside I/D cache, which may also be configured as SRAM and “stashing” memory to suit your application. Learn how "Stashing" and "Extraction" can be utilized with L2 cache to improve your system performance.
• Initialize the enhanced two-level Memory Management Unit to perform address translation, access control, and protection.
• Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, Quality of Service (QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol™.
• Configure and initialize the advanced 64-bit DDR2/DDR3 SDRAM memory controller with ECC support .
• Program the enhanced Local Bus Controller (eLBC) for local bus functions including Static memories, Flash memories, and Peripheral Input/Output operations.
• Configure and initialize the PCI Express controller modules.
• Program and initialize the DMA controller to transfer data between memory and Input/Output address spaces.
• Configure and learn how to initialize the P2020 from power-on reset.
• Understand how the Security Engine (SEC3.1) can off-load computation intensive security functions.
• Understand the serial RapidIO™ open standard and the RapidIO™ interconnect controller operation.

Note: Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Prerequisite:

Understanding PowerQUICC III processors (MPC85xx) is helpful. Also, familiarity with C language, with emphasis in data structure organization is advantageous.

However, student’s willingness and desire to learn is the most important factor.

Registration:

• Payment must be received no later than one week prior to start of course. The fee includes course notes, Rerence Manuals, and other applicable application notes and handouts.
  
• Seating is limited so please register early to get the desired place and time.
  
• Course cancellation is accepted one week prior to start of class. If the student cancelled one week prior to course he/she can elect to have course substitution for the same course at different date.
  
• Student substitution is accepted from same company.
  
• If student did not cancel one week prior to class the student will be charge the full rate.
  
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.