QorIQ Layerscape Platforms
The LS1012A processor integrates a single Arm® Cortex-A53 core running up to 800 MHz with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance in an ultra-small size envelope at 1W typical power dissipation. The LS1012A incorporates the same Trust Architecture and software compatibility of higher-tier QorIQ LS family devices, enabling scalable, secure applications that leverage a common 64-bit software platform.
The LS1012A training course is for software, hardware, firmware, and test designers who want to build battery-backed or USB-powered, space-constrained networking and IoT applications.
Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.
- Overview of the functional description of the LS1012A architecture.
- Learn and understand the ARM® Cortex®-A53 core programming model, register types, and instruction sets.
- Learn to configure the parity-protected L1 cache and ECC-protected 256KB L2 cache, along with CCI-400 for supporting cache coherency
- Write efficient exception service routines for the ARM Cortex core and ARM Interrupt Controller (GIC).
- Learn how to initialize the device from power-on reset, from Reset Configuration Word (RCW) to Pre-Boot Loader.
- Learn and understand Secure Boot and Trust Architecture.
- Learn the device internal memory map structure including configuring clock group clusters and PLLs.
- Understand the core Memory Management Unit MMU
- Understand and configure the enhanced DMA (eDMA) with up to 64 channels to perform various advanced data movement using Transfer Control Descriptors (TCDs). Another block called the DMAMUX multiplexer that allows up to 64 DMA request signals to be mapped to any 16 DMA channels.
- Learn and configure the 16-/8-bit DDR3L SDRAM memory controller(no ECC support).
- Learn the Packet Forwarding Engine (PFE) that provide the device with high performance Ethernet interfaces.
- Configure and initialize the PCI Express 3.0 controllers with RC and EP configurations, with 32-/64-bit address support.
- Understand how the Security Engine (SEC) can off-load computation intensive security functions.
- Learn and configure various communication blocks such as SPI, I2C, DUART.
- And much more...
Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.
Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.
- Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
- Seating is limited so please register early to get the desired place and time.
- If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
- Student substitution is accepted from same company.
- If student did not cancel one week prior to class the student will be charge the full rate.
- PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.