QorIQ Layerscape Platforms
he QorIQ LS1021A processor features an integrated LCD controller, CAN controller for implementing industrial protocols, DDR3L/4 running up to 1600 MHz, integrated security engine and QUICC Engine, and ECC protection on both L1 and L2 caches. The LS1021A processor is pin- and software-compatible with the QorIQ LS1020A and LS1022A processors.
The LS1021A training course is for software, hardware, firmware, and test designers who want to build fanless, small form factor enterprise and consumer networking applications.
Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.
- Overview of the functional description of the LS1021A architecture.
- Learn and understand the ARM® Cortex®-A7 core programming model, register types, and instruction sets.
- Learn to configure the ECC-protected 32KB L1 I-cache and D-cache and the ECC-protected 512KB shared L2 cache, along with CCI-400 for supporting cache coherency
- Write efficient exception service routines for the ARM Cortex core and ARM Interrupt Controller (GIC).
- Learn how to initialize the device from power-on reset, from Reset Configuration Word (RCW) to Pre-Boot Loader.
- Learn and understand Secure Boot and Trust Architecture.
- Learn the device internal memory map structure including configuring clock group clusters and PLLs.
- Understand the core Memory Management Unit MMU
- Understand and configure the enhanced DMA (eDMA) with up to 64 channels to perform various advanced data movement to slow bandwidth communication channels using Transfer Control Descriptors (TCDs). Another block called the DMAMUX multiplexer that allows up to 64 DMA request signals to be mapped to any 16 DMA channels.
- Learn and configure the 16-/8-bit DDR3L/4 SDRAM memory controller with ECC and interleaving support.
- Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, Quality of Service (QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol.
- Configure and initialize the popular communication modules such FlexCAN, SPI, I2C, UART interface.
- Configure and initialize the PCI Express 3.0 controllers running at Gen3 data rates (2.5 or 5Gbit/s).
- Understand how the QUICC Engine utilizes the SDMA and how to configure the enhanced Parameter RAM to execute microcode protocol such as HDLC.
- Understand how the Security Engine (SEC) can off-load computation intensive security functions.
- Learn and configure various communication blocks such as SPI, I2C, DUART.
- And much more...
Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.
Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.
- Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
- Seating is limited so please register early to get the desired place and time.
- If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
- Student substitution is accepted from same company.
- If student did not cancel one week prior to class the student will be charge the full rate.
- PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.