QorIQ Layerscape Platforms
The QorIQ® LS1043A processor is NXP's first quad-core, 64-bit Arm®-based processor for embedded networking. The LS1023A (two core version) and the LS1043A (four core version) deliver greater than 10 Gbps of performance in a flexible I/O package supporting fanless designs. This SoC is purpose-built solution for small-form-factor networking and industrial applications with BOM optimizations for economic low layer PCB, lower cost power supply and single clock design. The new 0.9V versions of the LS1043A and LS1023A deliver addition power savings for applications such as Wireless LAN and Power over Ethernet systems. The new 23x23 package options allow for pin compatible design which enable scaling to the LS1046A (quad A72 processor) or LS1088A (octal A53 core processor).
The QorIQ LS1043A delivers a performance boost over dual-core Arm 32-bit products and continues the QorIQ legacy of I/O flexibility and integrated QUICC Engine® for legacy glue-less HDLC, TDM or Profibus support.
The LS1043A or LS1023A architecture training course is for software, hardware, firmware, and test designers who want to build small form factor, fanless, enterprise and consumer networking applications.
Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.
- Overview of the functional description of the LS1043A and LS1023A architecture.
- Learn and understand the ARM® Cortex®-A53 core programming model, register types, and instruction sets.
- Learn to configure the ECC-protected 32KB L1 I-cache and D-cache and the ECC-protected 1MB shared L2 cache, along with CCI-400 for supporting cache coherency
- Write efficient exception service routines for the ARM Cortex core and ARM Interrupt Controller (GIC).
- Learn how to initialize the device from power-on reset, from Reset Configuration Word (RCW) to Pre-Boot Loader.
- Learn and understand Secure Boot and Trust Architecture.
- Learn the device internal memory map structure including configuring clock group clusters and PLLs.
- Understand the core Memory Management Unit MMU
- Understand and configure the enhanced DMA (eDMA) with up to 32 channels to perform various advanced data movement to slow bandwidth communication channels using Transfer Control Descriptors (TCDs). Another block called the DMAMUX multiplexer that allows up to 64 DMA request signals to be mapped to any 16 DMA channels.
- Learn and configure the 32-bit DDR3L/4 SDRAM memory controller with ECC and interleaving support.
- Learn and configure the Integrated Flash Controller IFC) module.
- Understand and configure the Data Path Acceleration Architecture (DPAA) hardware networking engine.
- Configure and initialize the PCI Express 3.0 controllers running at Gen3 data rates (2.5 or 5Gbit/s).
- Understand how the Security Engine (SEC) can off-load computation intensive security functions.
- Learn and configure various communication blocks such as SPI, I2C, DUART.
- And much more...
Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.
Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.
- Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
- Seating is limited so please register early to get the desired place and time.
- If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
- Student substitution is accepted from same company.
- If student did not cancel one week prior to class the student will be charge the full rate.
- PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.