The LS1046A and LS1026A processors integrate quad 64-bit Arm Cortex®-A72 cores with packet processing acceleration and high speed peripherals. They are pin-compatible with LS1023A, LS1043A and LS1088A SoC to provide performance scaling for 64- bit Arm, ranging from dual-A53 through octal-A53 to quad-A72 core processors, while maintaining hardware and software compatibility.

The LS1046A or LS1026A training course is for software, hardware, firmware, and test designers working on applications built on Layerscape architecture, the industry's first software-aware, core-agnostic communication applications. The cores can be configured to be used in either symmetric or asymmetric multiprocessing modes.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

• Overall overview of the functional descriptions of the LS1046A and LS1026A SoCdevices.
• Learn and understand the ARM® Cortex®-A72 core programming model, register types, and instruction sets.
• Configure and optimize the L1 and L2 caches.
• Write efficient exception service routines for the ARM Cortex core and ARM Interrupt Controller (GIC).
• Learn and configure how to initialize from power-on reset, from Reset Configuration Word (RCW) to Pre-Boot Loader.
• Learn and understand Secure Boot and Trust Architecture.
• Understand the expanded internal memory map structure including configuring clock group clusters and PLLs.
• Configure and initialize the System Memory Management Unit (SMMU) that provides Intermediate Physical Address (IPA) to Physical Address (PA) translation, and access controls such as peripherals and HW accelerators.
• Understand and configure the enhanced DMA (eDMA) with up to 32 channels to perform various advanced data movement using Transfer Control Descriptors (TCDs). Another block called the DMAMUX multiplexer that allows up to 24 DMA request signals to be mapped to any 16 DMA channels.
• Learn and configure the 64/72, 32/40-bit DDR4 SDRAM memory controllers with ECC error detection and correction support. Debug your memory controller drivers by configuring the onboard HW error injector.
• Learn and configure the Integrated Flash Controller (IFC).
• Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, Quality of Service (QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol.
• Configure and initialize the PCI Express 3.0 controllers with RC and EP configurations, with 32-bit address support.
• Learn and understand the Data Path Acceleration Architecture (DPAA) which parses, clasifies, and distributes ethernet frame, along with its hardware accelerator supports such as QMan, BMan, and Security and Encryption Engine (SEC) modules.
• Learn and configure the QUICC Engine block. The QUICC Engine is a complex communication IP with its own 32-bit RISC processor, its own serial DMAs, and its own Universal Communication Controllers (UCCS) to support various legacy communication protocols.
• Learn and configure various communication protocols such as SPI, I2C, DUART (Dual UART) and LPUART (Low Power UART).
• Learn how to manage and control heat flow across the device by understanding the Thermal Monitoring Unit (TMU) block.
• And much more...

Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

• Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
• Seating is limited so please register early to get the desired place and time.
• If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
• Student substitution is accepted from same company.
• If student did not cancel one week prior to class the student will be charge the full rate.
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.