MPC56xx 32-bit MCU
The MPC563xM MCU offers enhanced powertrain functionality for entry-level automotive and industrial applications. It also addresses the aggressive cost constraints of engine and transmission suppliers focused on emerging markets.
The MPC563xM architectural training course is designed for software, hardware, firmware, test engineers, and developers who want to build and test cost effective powertrain entry-level for automotive and industrial applications.
Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.
The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.
- Overview of the MPC563xM silicon systems, its memory map, and MPC56xx Roadmap.
- Understand the e200z3 programming models, register types, and usages.
- Learn the e200z3 basic integer/floating/load/store instruction sets, branches, subroutine calls, synchronizing instructions, and simplified mnemonics pertaining to UISA and VEA Power Architecture Instruction Sets.
- Learn and understand how the e200z3 access operand in memory, if not done correctly you may be accessing the wrong memory or peripheral locations
- Learn the e200z3 Variable Length Encoding (VLE) instruction set - an extension to the Book E Architecture to reduce code footprint by up to 30%.
- Configure the e200z3 Memory Management Unit (MMU) for address translation, access control, and memory protections. No more complicated MMU table walk!
- Write efficient exception service routines and configure the Programmable Interrupt Controller (PIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.
- Configure Boot-Assist Module (BAM) and ways of handling sources of system reset.
- Learn how to access internal SRAM and Flash memories.
- Configure and initialize the External Bus Interface (EBI), including memory controller.
- Configure and initialize the enhanced DMA (eDMA) to transfer data between I/O peripherals and memory via the crossbar switch (XBAR).
- Learn how to initialize the enhanced MIOS (eMIOS) for various timer modes to drive actuators, motors, and monitor input signals
- Configure and initialized the enhanced QADC (eQADC) to measure analog signals using various scan modes, various trigger mechanisms, various interrupt schemes, and various digital data formats. Two independent ADCs with up to 12-bit A/D resolution.
- Configure and initialize the popular communication modules such as FlexCAN, eSCI, and DSPI interfaces.
- Understand and configure the enhanced TPU2 (eTPU2) timing functions enables more sophisticated timing functions and can operate in parallel of the host processor.
Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.
Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.
- Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
- Seating is limited so please register early to get the desired place and time.
- If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
- Student substitution is accepted from same company.
- If student did not cancel one week prior to class the student will be charge the full rate.
- PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.