MPC5674F is based on the 32-bit Power Architecture technology (e200z7 CPU) with fast 16KB L1 harvard cache. The enhanced eTPU and eMIOS perform complex I/O timing functions. The eDMA and cross bar switch (XBAR) improve data movement within the silicon. Other modules are included such as eQADC, DSPI, eSCI, FLEXRAY, FlexCAN, Boot Assist Module (BAM) and embedded memories (up to 4MB Flash and up to 256KB of SRAM), and much more.

The MPC5674F architectural training course is designed for software, hardware, firmware, test engineers, and developers who want to build and test fuel-efficient engines that meet stricker government-mandated emission standards by enabling precise control engine events, such as combustion, without sacrificing performance.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the MPC5674F silicon systems and Roadmap.
• Learn the latest e200z7 Power Architecture programming model, register types, Signal Processing Unit (SPE2), and Variable Length Encoding (VLE)
• Review e200z7 core instruction set, branches, subroutine calls, simplified mnemonics, including the new SPE instruction features.
• Write efficient exception service routines for the e200z7 core and Interrupt Controller (INTC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical resources using HW or SW vector mode.
• Configure and optimize the e200z7 L1 cache with new APU cache locking instructions.
• Initialize the improved and simplified Memory Management Unit (MMU) to perform address translation, access control, and protection. No more complicated table walk!
• Configure and initialize the External Bus Interface (EBI), including memory controller, bus monitor, arbiter and various external pins needed to communicate to external peripherals.
• Understand and configure some of the enhanced TPU (eTPU) timing functions with new and easy C-like instructions. The eTPU enables more sophisticated timing functions and simplify angle domain scheduling using its powerful angle clock hardware.
• Learn how to initialize the enhanced MIOS (eMIOS) for various timer modes to drive actuators, motors, and monitor input signals.
• Configure and initialize the enhanced DMA (eDMA) to transfer data between on-chip I/O peripherals and on-chip memory via the crossbar switch (XBAR). eDMA module does not have external pins.
• Configure and initialized the enhanced QADC (eQADC) to measure analog signals using various scan modes, various trigger mechanisms, various interrupt schemes, and various digital data formats. Independent eADCs with up to 12-bit A/D resolution.
• Initialize and configure the EBI to interface to external memories, I/O peripherals, ASIC or FPGA devices.
• Configure and initialize the enhanced SCI (eSCI) to perform serial communication using full-duplex/half-duplex, standard/non-standard baud rates, error checking with LIN and DMA supports.
• Configure and initialize the popular FlexCAN a serial communication protocols used for automotive and industrial control applications.
• Learn how to initialize from power-on reset. Understand and use the Boot Assist Module (BAM) for device operation after reset, but before user application. BAM is a block of read-only memory resident in the device.
• Understand and learn the FlexRay controller module that is compliant with the FlexRay Communications System Protocol Specification and FlexRay Communications System Electrical Physical Layer Specification.

Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

• Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
• Seating is limited so please register early to get the desired place and time.
• If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
• Student substitution is accepted from same company.
• If student did not cancel one week prior to class the student will be charge the full rate.
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.