MPC5746M is part of the SafeAssure program, which is designed to help system manufacturers achieve compliance with functional safety standards such as ISO 26262 for ASIL-D safety integrity. In order to minimize additional software and module level features to reach this target, on-chip redundancy is offered for the critical components of the microcontroller (multiple CPU computational cores with delayed lock-step, I/O processor core, DMA controller, Interrupt controller, dual crossbar bus system, memory protection unit, fault collection unit, flash memory and RAM controllers, peripheral bus bridge, system and watchdog timers and end to end ECC).

The MPC5746M architectural training course is designed for software, hardware, firmware, test engineers, and developers who want to build and test high-end automotive and industrial high-end products which meet functional safety standards such as ISO 26262 for ASIL-D safety integrity.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Architectural overview of the MPC5746M silicon systems and MPC5700 Roadmap.
• Understand system architecture and features
• Power Architecture programming model for the multi core e200z4 together with Variable-Length Encoding (VLE) and Light Signal Processing Unit (LSP.
• Understand On-chip tightly-coupled memories including I-cache and D-cache.
• Understand Level 1 and level 2 memory organization and operation.
• Configure core Memory Protection Unit (CMPU) and System Memory Protection Unit (SMPU).
• Initialize Crossbar switched and bus master arbitration sequence.
• Write efficient Exceptions and Interrupt routines.
• Configure Interrupt Controller and Context Switching with new instructions, semaphore block.
• Configure system clock and other PLL operation.
• Boot-Assist Flash (BAF boot sequence).
• Understand system reset sources and reset handling.
• System initialization at start-up and other device configuration with low power capabilities.
• Configure and initialize the enhanced DMA (eDMA) to transfer data between I/O peripherals and memory.
• Configure various serial interfaces such as FlexRay, DSPI, microsecond channel (TSB), CRC generator.
• In-depth understanding of various Timers inside the device.
• In-depth understanding of Functinal Safety which includes two cores running in lock-step for safety integrity, with Redundancy Checkers (RCCU), Self-Test Control Unit (STCU2) and meeting the ASIL 26262 Standards.
• And much more...

Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

• Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
• Seating is limited so please register early to get the desired place and time.
• If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
• Student substitution is accepted from same company.
• If student did not cancel one week prior to class the student will be charge the full rate.
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.