The MPC5777M Power Architecture® MCU targets high-end industrial and powertrain applications that meet next-generation advanced engine control, functional safety, and security requirements. It provides task flexibility and parallel processing by leveraging the I/O processor to offload computational cores. Also deters software hacking and aftermarket tuning (which affects unauthorized warranty returns) with next-generation security protection.

The MPC5777M architectural training course is designed for software, hardware, firmware, test engineers, and developers who want to build and test high-end industrial and powertrain applications for next-generation advanced engine control, functional safety, and security requirements.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Architectural overview of the MPC5777M silicon systems and MPC5700 Roadmap.
• Understand system architecture and features
• Power Architecture programming model for the e200z7 and e200z4 together with Variable-Length Encoding (VLE) and Light Signal Processing Unit (LSP.
• Understand On-chip tightly-coupled memories including I-cache and D-cache.
• Understand Level 1 and level 2 memory organization and operation.
• Configure core Memory Protection Unit (CMPU) and System Memory Protection Unit (SMPU).
• Initialize Crossbar switched and bus master arbitration sequence.
• Write efficient Exceptions and Interrupt routines.
• Configure Interrupt Controller and Context Switching with new instructions, semaphore block.
• Configure system clock and other PLL operation.
• Boot-Assist Flash (BAF boot sequence).
• Understand system reset sources and reset handling.
• System initialization at start-up and other device configuration with low power capabilities.
• Configure and initialize the enhanced DMA (eDMA) to transfer data between I/O peripherals and memory.
• Configure various serial interfaces such as FlexRay, DSPI, microsecond channel (TSB), CRC generator.
• Configure various Memories (Flash, SRAM) and ADCs (SAR_ADCs and SD_ADC) and system timers.
• In-depth understanding of Generic Timer Module (GTM) with various modes of operations (TIM, TOM, ATOM) and vaious angle clock operation.
• In-depth understanding of Functinal Safety which includes two cores running in lock-step for safety integrity, Fault Control and Collection Unit (FCCU), Self-Test Control Unit (STCU2) and meeting the ASIL 26262 Standards.
• And much more...

Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

• Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
• Seating is limited so please register early to get the desired place and time.
• If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
• Student substitution is accepted from same company.
• If student did not cancel one week prior to class the student will be charge the full rate.
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.