The P1020 and P1011 communications processors, offers the value of extensive integration and extreme power for a wide variety of applications in the networking, telecom, aerospace, defense and industrial markets. The series provides dual-and single-core solutions for the 533 MHz to 800 MHz performance range, along with advanced security and a rich set of interfaces delivered on 45 nm technology for a low-power implementation.
The P1020 and P1011 architecture training course is designed for software, hardware, firmware, test engineers, and developers who want to build possible multiprocessing communication systems for networking, telecom, aerospace, defense and industrial markets.
Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.
The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.
- Overview of the overall functional descriptions of the P10xx architecture.
- Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
- Learn the e500 core programming model, register types, and usages.
- Review e500 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
- Write efficient exception service routines for the new e500 and Programmable Interrupt Controller (PIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.
- Configure and optimize the e500v2 L1 caches and the L2 look-aside cache/static SRAM block (512Kbytes) to suit your application. Understand how "Stashing" and "Extraction" can be utilized with L2 cache to improve system performance.
- Initialize the enhanced two-level Memory Management Unit to perform address translation, access control, and protection.
- Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP
offload, Quality of Service(QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol™.
- Configure and initialize the advanced main memory controller for DDR2/DDR3 type memories.
- Program the second memory controller using Local Bus Controller(LBC) for local bus functions including SDRAM (DRAM), SRAM, flash EPROM, and EPROM memory operations.
- Configure and initialize the PCI Express controller modules.
- Configure and initialize the DMA controller.
- Learn how to initialize the P10x0 from power-on reset.
- Understand how the Security Engine (SEC) can off-load computation intensive security functions.
- And much more...
Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.
Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.
- Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
- Seating is limited so please register early to get the desired place and time.
- If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
- Student substitution is accepted from same company.
- If student did not cancel one week prior to class the student will be charge the full rate.
- PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.