The P4080 was the flagship product for the QorIQ family when it was first introduced to the market. It provided the foundation upon which the P5, P3, P2 and P1 processor families were built. In addition to those families, P4080 expanded its portfolio with the P4040 and P4081. These processors provide a performance, power and price to meet a broad spectrum of high-performance applications. It combines four to eight Power Architecture e500mc cores operating at frequencies up to 1.5 GHz with high-performance data path acceleration logic and network and peripheral bus interfaces designed for 45 nm technology to deliver high-performance, next-generation networking services in a very low-power envelope.

The P4040, P4080, P4081 architecture training course is designed for software, hardware, firmware, test engineers, and developers who want to design systems that are compute intensive, I/O intensive or both for networking, telecom, aerospace, defense and industrial markets.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional descriptions of the P4040, P4080, P4081 architectures.
• Learn the latest e500mc core programming model, register types, and usages.
• Configure and optimize the L1, L2, L3 caches with new Stashing, CoreNet data intervention, Write Shadow Mode, parity generation and checking to maximize performance.
• Initialize the enhanced demand-paged virtual two-level Memory Management Unit with Hypervisor mode operations to perform address translation, access control, and protection.
• Write efficient exception service routines for the new e500mc and the Multicore Programmable Interrupt Controller (MPIC) by understanding new interrupt instructions, new interrupt features such as interrupt proxy, error reporting, new NMI, Doorbell, interrupts and multicore interrupt model.
• Learn and configure how to initialize from power-on reset, from RCW, and from Pre-Boot Loader.
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
• Configure the PAMU (Peripheral Access Management Unit), which provides address translation and access control for all bus masters in the system.
• Understand and configure the Buffer Manager which provides a centralized resource management function for memory buffer (data).
• Understand and configure the Queue Manager which provides queuing of data betwen the network interface, HW off-load accelerators, and cores in a multicore devices.
• Understand and configure the Frame Manager. It is a functional unit that combines the Ethernet network interface with packet allotment logic to provide intelligent distribution queuing decision for incoming traffic.
• Configure the initialize the Ethernet ports: A10-Gigabit Ethernet (10GEC) with XAUI transmit and receive interfaces; and the Data Three Speed Ethernet Controller (dTSEC) for 10/100/1000 Mbps operations.
• Learn and configure the DDR2/3 SDRAM memory controllers with ECC support. Each memory controller has support for error injection for debugging and testing.
• Program the Enhanced Local Bus Controller (eLBC) using GPCM machines for static memories or peripheral devices, FCM machines for NAND Flash, and UPM machines for devices that require re-fresh.
• Configure and initialize the PCI Express 2.0 controllers with RC and EP configurations, with 32- and 64-bit address support.
• Program and initialize the 4-channel DMA controllers to transfer data between memory and Input/Output address spaces with 256 byte block transfer, externally-controlled transfer pins.
• Understand how the Security Engine (SEC) can off-load computation intensive security functions i.e. cryptographic engine accelerators such as Public Key, DES, and AES.
• Understand the serial RapidIO interconnect controller operation.
• Understand the Pattern Matching Engine operation.

Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

• Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
• Seating is limited so please register early to get the desired place and time.
• If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
• Student substitution is accepted from same company.
• If student did not cancel one week prior to class the student will be charge the full rate.
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.