The QorIQ P5 family delivers scalable, 64-bit processing with single-, dual-, and quad-core devices. With frequencies scaling up to 2.2 GHz, a tightly coupled cache hierarchy for low latency, and integrated hardware acceleration, the P5040 (quad-core) and P5021 (dual-core) devices are ideally suited for compute intensive, power-conscious control plane applications
The P5040 architecture training course is designed for software, hardware, firmware, test engineers, and developers who want to design, for example, control processors in applications such as routers, switches, internet access devices, firewall and other packet filtering processors, network attached storage, storage area networks, imaging and general-purpose embedded computing.
Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.
The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.
- Overview of the overall functional descriptions of the P5040 and P5021 architectures.
- Learn the latest e5500 core programming model, register types, and usages.
- Configure and optimize the L1, L2, L3 caches with new Stashing, CoreNet data intervention, Write Shadow Mode, parity generation and checking to maximize performance.
- Initialize the enhanced demand-paged virtual two-level Memory Management Unit with Hypervisor mode operations to perform address translation, access control, and protection.
- Write efficient exception service routines for the new e5500 and the Multicore Programmable Interrupt Controller (MPIC) by understanding new interrupt instructions, new interrupt features such as interrupt proxy, error reporting, new NMI, Doorbell, interrupts and multicore interrupt model.
- Learn and configure how to initialize from power-on reset, from RCW, and from Pre-Boot Loader.
- Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
- Configure the PAMU (Peripheral Access Management Unit), which provides address translation and access control for all bus masters in the system.
- Understand the Frame Manager as it relates to Ethernet MAC controls.
- Configure the DataPath Three Speed Ethernet Controller (dTSEC) for 10/100/1000 Mbps operations.
- Learn and configure the DDR3/3L SDRAM memory controllers with ECC support. Each memory controller has support for error injection for debugging and testing.
- Program the Enhanced Local Bus Controller (eLBC) using GPCM machines for static memories or peripheral devices, FCM machines for NAND Flash, and UPM machines for devices that require re-fresh.
- Configure and initialize the PCI Express controllers with RC and EP configurations, with 32- and 64-bit address support.
- Program and initialize the 4-channel DMA controllers to transfer data between memory and Input/Output address spaces with 256 byte block transfer, externally-controlled transfer pins.
- And much more...
Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.
Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.
- Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
- Seating is limited so please register early to get the desired place and time.
- If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
- Student substitution is accepted from same company.
- If student did not cancel one week prior to class the student will be charge the full rate.
- PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.