The dual-core T1024 and T1023 and single-core T1014 and T1013 communications processors combine 64-bit cores, built on Power Architecture technology, with high-performance Data Path Acceleration Architecture (DPAA) and network peripheral bus interfaces required networking, telecommunications and industrial networked applications. The QorIQ T Series platform offers optimized features for the industrial market, including a display interface unit for HMI, the QUICC Engine for industrial protocol offload and ECC support for high reliability ALWAYS-ON applications.

The T1024/T1023 and T1014/T1013 architecture training course is designed for software, hardware, firmware, test engineers, and developers who want to build impressive single or dual core performance for cost and power sensitive networking and industrial systems. Both versions offer an excellent software compatible 64-bit and I/O upgrade path for the popular QorIQ P10xx family of 32-bit communications processors.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional descriptions of the T1024/T1023 and T1014/T1013 architectures.
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
• Learn the e5500 core programming model, register types, and usages.
• Review e5500 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
• Write efficient exception service routines for the new e5500 and Multicore Programmable Interrupt Controller (MPIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.
• Configure and optimize the e5500 L1 cache, L2 cache, and L3 look-aside cache/static SRAM block to suit your application. Understand how "Stashing" and "Extraction" can be utilized with L2 cache to improve system performance.
• Initialize the enhanced two-level Memory Management Unit to perform address translation, access control, and protection.
• Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, Quality of Service(QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol™.
• Configure and initialize the advanced main memory controller for DDR3L/DDR4 type memories.
• Program the second memory controller using Local Bus Controller(LBC) for local bus functions including SDRAM (DRAM), SRAM, flash EPROM, and EPROM memory operations.
• Configure and initialize the PCI Express controller modules.
• Configure and initialize the DMA controller.
• Learn how to initialize the device from power-on reset.
• Understand how the Security Engine (SEC) can off-load computation intensive security functions.
• Learn how to configure the QUICC Engine for various communication protocol microcode package such as ATM, HDLC, UART abd others.
• And much more...

Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

• Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
• Seating is limited so please register early to get the desired place and time.
• If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
• Student substitution is accepted from same company.
• If student did not cancel one week prior to class the student will be charge the full rate.
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.