The T1040 quad-core and the T1020 dual-core communication processors support two or four integrated 64-bit e5500 Power Architecture processor cores with high-performance data path acceleration architecture (DPAA) and network peripheral interfaces required for networking and telecommunications.

The T1040 and T1020 are the industry's first 64-bit embedded processors with an integrated gigabit Ethernet switch. The T family is ideally suited for use in mixed control and data plane applications such as fixed routers, switches, integrated access devices, firewall and other packet filtering applications, as well as general-purpose embedded computing. Its high level of integration offers significant performance benefits and greatly helps to simplify hardware and software design.

The T1040 or T1020 architecture training course is for software, hardware, firmware, and test designers, who want to build many system communication application needs. The cores can be configured to be used in either AMP or SMP modes, perhaps with Hypervisor features, which allow different cores to run different operating systems with secure partitioning and perhaps managing a few virtual machines is one such application. Telecom, Datacom, wireless infrastructure, and mil/aerospace are other applications.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional descriptions of the T1042/T1022 and T1040/T1020 architectures.
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
• Learn the e5500 core programming model, register types, and usages.
• Review e5500 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
• Write efficient exception service routines for the new e5500 and Multicore Programmable Interrupt Controller (MPIC) by understanding the innovative exception processing function with built-in interrupt priorities, separate critical, non-critical, and machine check interrupts.
• Configure and optimize the e5500 L1 cache, L2 cache, and L3 look-aside cache/static SRAM block to suit your application. Understand how "Stashing" and "Extraction" can be utilized with L2 cache to improve system performance.
• Initialize the enhanced two-level Memory Management Unit to perform address translation, access control, and protection.
• Configure the enhanced eTSEC for 10/100/1000 Mbps Ethernet using PHYs and FIFOs operation, TCP/IP offload, Quality of Service(QoS) support, interrupt coalescing, power management using AMD Magic Packet protocol™.
• Configure and initialize the advanced main memory controller for DDR3L/DDR4 type memories.
• Program the second memory controller using Local Bus Controller(LBC) for local bus functions including SDRAM (DRAM), SRAM, flash EPROM, and EPROM memory operations.
• Configure and initialize the PCI Express controller modules.
• Configure and initialize the DMA controller.
• Learn how to initialize the device from power-on reset.
• Understand how the Security Engine (SEC) can off-load computation intensive security functions.
• Learn how to configure the QUICC Engine for various communication protocol microcode package such as ATM, HDLC, UART abd others.
• And much more...

Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

• Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
• Seating is limited so please register early to get the desired place and time.
• If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
• Student substitution is accepted from same company.
• If student did not cancel one week prior to class the student will be charge the full rate.
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.