With frequencies scaling to 1.8 GHz, integrated 1Gbps and 10Gpbs Ethernet, hardware acceleration and advanced system peripherals, these products target applications that benefit from consolidation of control and data plane processing in a single SoC, such as services cards, microservers, ADCs, WOCs, intelligent NICS, RNC.

The T4240 or T4160, or T4080 architecture training course is for software, hardware, firmware, and test designers, who want to build very high-performance networking, telecom/datacom, data center, wireless infrastructure, and mil/aerospace applications utilizing four dual-threaded e6500 cores with AltiVec and DPAA hardware accelerator.

The cores can be configured to be used in either AMP or SMP modes, perhaps with Hypervisor features, which allow different cores to run different operating systems with secure partitioning and perhaps managing a few virtual machines is one such application.

Managers, system architects, and project leaders, are also encouraged to attend the class for an in-depth understanding of the SoC device.

The class will cover both the hardware and software aspect of the device. Each topic is self-contained. That is, both hardware and software materials are included to make the topic complete. The class consists of lectures and exercises.

• Overview of the overall functional descriptions of the T4240, T4160, and T4080 architectures.
• Understand the expanded internal memory map structure including Local Access Window (LAWs) and Inbound/Outbound Address Translation Mapping Units (ATMUs).
• Learn the 64-bit e6500 core programming model, register types, and usages.
• Review e6500 core instruction set, branches, subroutine calls, simplified mnemonics, and accessing operand in memory.
• Configure and optimize the e6500 harvard L1 cache, shared L2 cache.
• Initialize the enhanced two-level Memory Management Unit to perform address translation, access control, and protection.
• Write efficient exception service routines for the new e6500 and the Multicore Programmable Interrupt Controller (MPIC) by understanding new interrupt instructions, new interrupt features such as interrupt proxy, error reporting, new NMI, Doorbell, interrupts and multicore interrupt model.
• Learn and configure how to initialize from power-on reset, from RCW, from Pre-Boot Loader.
• Learn how to configure the e6500 cores for either AMP or SMP modes, perhaps with Hypervisor features, and allow different cores to run different operating systems.
• Learn and configure how to initialize from power-on reset, from RCW, from Pre-Boot Loader.
• Configure the PAMU (Peripheral Access Management Unit), which provides address translation and access control for all bus masters in the system.
• Understand and configure the Buffer Manager which provides a centralized resource management function for memory buffer (data).
• Understand and configure the Queue Manager which provides queuing of data betwen the network interface, HW off-load accelerators, and cores in a multicore devices.
• Understand and configure the Frame Manager. It is a functional unit that combines the Ethernet network interface with packet allotment logic to provide intelligent distribution queuing decision for incoming traffic.
• Learn and configure the DDR3/3L SDRAM memory controllers with ECC support. Each memory controller has support for error injection for debugging and testing.
• Configure and initialize the PCI Express controllers with RC and EP configurations, with 32- and 64-bit address support.
• Program and initialize the 8-channel DMA controllers to transfer data between memory and Input/Output address spaces with 256 byte block transfer, externally-controlled transfer pins.
• Understand how the Security Engine (SEC) can off-load computation intensive security functions i.e. cryptographic engine accelerators such as Public Key, DES, and AES.
• Understand the serial RapidIO interconnect controller operation.
• Understand the Pattern Matching Engine operation.
• And much more...

Total topics covered will vary depending on class size, student's background, and pace of the class. Our instructors are flexible to adapt and adjust topics to suit your requirements.

Understanding of basic microprocessor and microcontroller inner working are helpful. Also, familiarity with C language especially data structure organization is advantageous. However, the student willingness and desire to learn are the most important factors.

• Payment must be received no later than two weeks prior to start of course. The fee includes course note, reference manuals and applicable application notes.
• Seating is limited so please register early to get the desired place and time.
• If the student cancelled two weeks prior to course he/she can elect to have course substitution for the same course at different date.
• Student substitution is accepted from same company.
• If student did not cancel one week prior to class the student will be charge the full rate.
• PhoenixMicro Inc. has the right to cancel courses one week prior to start date due to low enrollment.